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Silicon Labs /SiM3_NRND /SIM3L168_A /PBCFG_0 /XBAR0

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Interpret as XBAR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)USART0EN 0 (DISABLED)USART0FCEN 0 (DISABLED)USART0CEN 0 (DISABLED)DMA0T0EN 0 (DISABLED)DMA0T1EN 0 (DISABLED)IDAC0TEN 0 (DISABLED)SPI0EN 0 (DISABLED)SPI0NSSEN 0 (NONE)EPCA0EN 0 (DISABLED)EECI0EN 0 (DISABLED)I2C0EN 0 (DISABLED)CMP0SEN 0 (DISABLED)CMP0AEN 0 (DISABLED)CMP1SEN 0 (DISABLED)CMP1AEN 0 (DISABLED)TMR0CTEN 0 (DISABLED)TMR0EXEN 0 (DISABLED)TMR1CTEN 0 (DISABLED)TMR1EXEN 0 (DISABLED)SARADC0TEN 0 (DISABLED)AHBEN 0 (DISABLED)XBAR0EN

SARADC0TEN=DISABLED, SPI0NSSEN=DISABLED, IDAC0TEN=DISABLED, USART0CEN=DISABLED, TMR1EXEN=DISABLED, TMR0EXEN=DISABLED, EPCA0EN=NONE, SPI0EN=DISABLED, CMP1AEN=DISABLED, TMR1CTEN=DISABLED, TMR0CTEN=DISABLED, AHBEN=DISABLED, I2C0EN=DISABLED, CMP0SEN=DISABLED, USART0FCEN=DISABLED, USART0EN=DISABLED, DMA0T1EN=DISABLED, DMA0T0EN=DISABLED, XBAR0EN=DISABLED, EECI0EN=DISABLED, CMP0AEN=DISABLED, CMP1SEN=DISABLED

Description

Crossbar 0 Control

Fields

USART0EN

USART0 Enable.

0 (DISABLED): Disable USART0 RX and TX on Crossbar 0.

1 (ENABLED): Enable USART0 RX and TX on Crossbar 0.
USART0FCEN

USART0 Flow Control Enable.

0 (DISABLED): Disable USART0 flow control on Crossbar 0.

1 (ENABLED): Enable USART0 flow control on Crossbar 0.
USART0CEN

USART0 Clock Signal Enable.

0 (DISABLED): Disable USART0 clock on Crossbar 0.

1 (ENABLED): Enable USART0 clock on Crossbar 0.
DMA0T0EN

DMA Trigger 0 Enable.

0 (DISABLED): Disable the DMA trigger 0 on Crossbar 0.

1 (ENABLED): Enable the DMA trigger 0 on Crossbar 0.
DMA0T1EN

DMA Trigger 1 Enabled.

0 (DISABLED): Disable the DMA trigger 1 on Crossbar 0.

1 (ENABLED): Enable the DMA trigger 1 on Crossbar 0.
IDAC0TEN

IDAC0 Trigger Enable.

0 (DISABLED): Disable the IDAC0 trigger on Crossbar 0.

1 (ENABLED): Enable the IDAC0 trigger on Crossbar 0.
SPI0EN

SPI0 Enable.

0 (DISABLED): Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.

1 (ENABLED): Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.
SPI0NSSEN

SPI0 NSS Pin Enable.

0 (DISABLED): Disable SPI0 NSS on Crossbar 0.

1 (ENABLED): Enable SPI0 NSS on Crossbar 0.
EPCA0EN

EPCA0 Channel Enable.

0 (NONE): Disable all EPCA0 channels on Crossbar 0.

1 (CEX0_0): Enable EPCA0 CEX0 on Crossbar 0.

2 (CEX0_1): Enable EPCA0 CEX0 and CEX1 on Crossbar 0.

3 (CEX0_2): Enable EPCA0 CEX0, CEX1, and CEX2 on Crossbar 0.

4 (CEX0_3): Enable EPCA0 CEX0, CEX1, CEX2, and CEX3 on Crossbar 0.

5 (CEX0_4): Enable EPCA0 CEX0, CEX1, CEX2, CEX3, and CEX4 on Crossbar 0.

6 (CEX0_5): Enable EPCA0 CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 on Crossbar 0.
EECI0EN

EPCA0 ECI Enable.

0 (DISABLED): Disable EPCA0 ECI on Crossbar 0.

1 (ENABLED): Enable EPCA0 ECI on Crossbar 0.
I2C0EN

I2C0 Enable.

0 (DISABLED): Disable I2C0 SDA and SCL on Crossbar 0.

1 (ENABLED): Enable I2C0 SDA and SCL on Crossbar 0.
CMP0SEN

Comparator 0 Synchronous Output (CMP0S) Enable.

0 (DISABLED): Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.

1 (ENABLED): Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
CMP0AEN

Comparator 0 Asynchronous Output (CMP0A) Enable.

0 (DISABLED): Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.

1 (ENABLED): Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
CMP1SEN

Comparator 1 Synchronous Output (CMP1S) Enable.

0 (DISABLED): Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.

1 (ENABLED): Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
CMP1AEN

Comparator 1 Asynchronous Output (CMP1A) Enable.

0 (DISABLED): Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.

1 (ENABLED): Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
TMR0CTEN

TIMER0 T0CT Enable.

0 (DISABLED): Disable TIMER0 CT on Crossbar 0.

1 (ENABLED): Enable TIMER0 CT on Crossbar 0.
TMR0EXEN

TIMER0 T0EX Enable.

0 (DISABLED): Disable TIMER0 EX on Crossbar 0.

1 (ENABLED): Enable TIMER0 EX on Crossbar 0.
TMR1CTEN

TIMER1 T1CT Enable.

0 (DISABLED): Disable TIMER1 CT on Crossbar 0.

1 (ENABLED): Enable TIMER1 CT on Crossbar 0.
TMR1EXEN

TIMER1 T1EX Enable.

0 (DISABLED): Disable TIMER1 EX on Crossbar 0.

1 (ENABLED): Enable TIMER1 EX on Crossbar 0.
SARADC0TEN

SARADC0 Trigger Enable.

0 (DISABLED): Disable SARADC0 conversion start trigger on Crossbar 0.

1 (ENABLED): Enable SARADC0 conversion start trigger on Crossbar 0.
AHBEN

AHB Clock Output Enable.

0 (DISABLED): Disable the AHB Clock / 16 output on Crossbar 0.

1 (ENABLED): Enable the AHB Clock / 16 output on Crossbar 0.
XBAR0EN

Crossbar 0 Enable.

0 (DISABLED): Disable Crossbar 0.

1 (ENABLED): Enable Crossbar 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data